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Megahunt has cooperated with Wiznet to unveil the MH2153A with W5500 Ethernet transceiver embedded

In April 2025, Megahunt and Wiznet formally announced to deliver an MCU of Arm Cortex M3, with:


True Random Number Generator, Hardware Encryption Algorithm Unit, 1024KB Flash, 96KB SRAM, 10/100M Ethernet MAC and PHY, Hardware Internet controller with an integrated full TCP/IP stack, USB, CAN, 17 Timers, 3 ADCs, 2 DACs, up to 12 communication interfaces, and even more resources.

This device part number is MH2153A, with two packages: QFN100 (MH2153AL) and QFN68(MH2153AQ).

Features:
■ Core: 32-bit Arm Cortex-M3 core
− Up to 216MHz operation frequency,2.54 DMips/MHz (CoreMark1.0)
− Single-cycle multiplication and hardware division
■ Memories
− 1024K bytes of Flash memory
− 96K bytes of SRAM
■ Clock, reset and supply management
− 2.0~3.6V application supply and I/Os
− POR, PDR, and programmable voltage detector (PVD)
− 4~16MHz crystal oscillator
− Internal 8MHz factory-trimmed RC
− Internal 40kHz RC oscillator with calibration
− 32kHz RTC oscillator with calibration
■ Low power
− Sleep, Stop and Standby modes
− supply for RTC and backup registers
■ 3 x 12-bit, 1 µs A/D converters (up to 12 channels)
− Conversion range: 0 to 3.6V
− Temperature sensor
■ 2 x 12-bit D/A converters
■ DMA:12-channel DMA controller
■ Ethernet:10/100M Ethernet MAC and PHY
− Supports Hardwired TCP/IP Protocols: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
− Supports 8 independent sockets simultaneously
− Internal 32K bytes Memory for Tx/Rx Buffers
− 10BaseT/100BaseTX Ethernet PHY embedded
− Support Auto Negotiation (Full and half duplex, 10 and 100-based)
− LED outputs (Full/Half duplex, Link, Speed, Active)
■ Debug mode
− Serial wire debug (SWD) & JTAG interfaces
− Embedded Tracking Module (ETM)
■ I/O ports
− 66(MH2153AL) / 36(MH2153AQ) multi-function bidirectional I/O ports, all mappable on 16 external interrupts
− All GPIOs can be forced to configure pull-up and pull-down resistors
■ Enhanced CRC calculation unit
■ 17 Timers
■ Up to 12 communication interfaces
− Up to 2 x I2C interfaces (support SMBus/PMBus)
− Up to 5(MH2153AL) / 3(MH2153AQ) x USARTs
− Up to 2 x SPIs, 1 multiplexed with I2S interface
− CAN interface (2.0B Active)
− USB 2.0 full-speed interface (Optional internal 1.5K pull-up resistor)
− SDIO interface (only MH2153AL)
■ Hardware encryption algorithm unit
− Built-in hardware algorithm(DES、AES、SHA)
− Provide a complete high-performance algorithm library
■ TRNG:generate sequence of true random numbers
− Four independent true random sources, which can be configured individually
− 128bit random numbers can be generated at one time
− Optional digital post-processing function
− Attack detection
■ SENSOR:voltage & temperature sensor alarm
− VBAT and VDD voltage can be detected independently
− Provide temperature detection sensor
− Optional reset or interrupt after alarm